1. Field of the Invention:
The present invention relates to a method of and equipment for manufacturing a semiconductor device laying emphasis on an insulating film to be used for insulation between electrodes.
2. Description of the Related Art:
With reference to a method of leveling an interlayer insulating film to be applied in a wiring layer of the semiconductor device, a few composite processes have been proposed (for example, Semicon News: June 1989, pp. 62-67).
A representative method of leveling the interlayer insulating film will be described with reference to FIG. 1(a) to (d).
First, as shown in FIG. 1(a), aluminum electrodes 303 are formed on a ground insulating film (a silicon dioxide film formed by a thermal oxidation method or a CVD method, or a silicon nitride film formed by a CVD method) 302 provided on the surface of a semiconductor substrate 301. An insulating film 304 made of, for example, a silicon dioxide film, silicon nitride film or silicon oxynitride (SiON) film about 1 .mu.m thick is formed by a plasma CVD method so as to cover the ground insulating film 302 and aluminum electrodes 303.
Then, as shown in FIG. 1(b), a SOG (Spin-on-Glass) film 305 is applied to the thus-produced flat reference wafer to a thickness in the range of 0.2 .mu.m to 0.5 .mu.m.
Next, as shown in FIG. 1(c), a dry etching method is employed to dry etch the SOG film 305 so as to leave the SOG film only on the side walls of the aluminum electrodes 303 and in small gaps therebetween.
Next, an annealing operation at about 370.degree. C. is applied to the SOG film 305 in order to vaporize the contained moisture and to solidify the SOG film 305.
Finally, as shown in FIG. 1(d), an interlayer insulating film 306 made up of, for example, a silicon dioxide film, silicon nitride film or silicon oxynitride (SiON) film about 1 .mu.m thick is grown thereon by the plasma CVD method to complete the leveling of the interlayer insulating film.
With the above-described manufacturing method, since the SOG film 305 remains on the side walls of the aluminum electrodes 303, unevenness on the covered interlayer insulating film 306 is improved. As a result, defects such as cracks or disconnections in the metal wiring of a second layer formed in a succeeding process will be reduced. In recent studies, methods for improving the flatness of the interlayer insulating film without using an SOG film have been investigated. For example, there is a method for leveling the surface by grinding the surface of the interlayer insulating film as disclosed in Japanese Patent Laid Open 92-162530.
The above manufacturing method will be described with reference to FIG. 2(a) to FIG. 2(c).
As shown in FIG. 2(a), aluminum electrodes 403 which serve as the metal wiring are first formed on a 10 semiconductor substrate 401 which has a ground insulating film 402 formed thereon in advance, following which a silicon dioxide film (hereinafter referred to as a P--SiO film) 407 2 to 5 .mu.m thick is formed thereon by means of a plasma CVD method.
Next, as shown in FIG. 2(b), the P--SiO film 407 is ground from its outermost surface until its thickness on the aluminum electrode 403 is within the range of 0.5 to 1.0 .mu.m, thereby producing a wafer with a completely flat surface.
Next, as shown in FIG. 2(c), a silicon nitride film (hereinafter referred to as a P--SiN film) 408 0.2 .mu.m to 0.5 .mu.m thick is grown thereon as a dampproof film by means of a plasma CVD method. Since the surfaces of the P--SiO film 407 and P--SiN film 408, which function as interlayer insulating films, are made perfectly flat, defects such as cracks or disconnections in the metal wiring of the second metal layer to be formed in a succeeding process are greatly reduced, thereby improving the reliability of the semiconductor device.
However, the above-described conventional manufacturing method for leveling the interlayer insulating film has the following defects when using an SOG film.
First, to improve the reliability of the metal wiring of the second wiring layer, the surface of the interlayer insulating film must be sufficiently flat. To achieve this degree of flatness, the SOG film must remain in sufficient thickness on the side walls of the aluminum electrode 303. On the other hand, if the SOG film 305 is thickly coated, cracks tend to be generated in the SOG film during annealing for burning and solidifying the film. Maintaining proper control of the manufacturing conditions is therefore very difficult.
Second, since the SOG film 305 contains considerable moisture, high-temperature annealing is indispensable to evaporate the moisture and solidify the film. However, since the SOG film 305 has been coated on the aluminum electrode 303, the annealing temperature must be limited to 400.degree. C. or less to prevent melting, corrosion or deterioration of the aluminum electrode 303. However, because it is impossible to completely remove the moisture contained in the SOG film 305 at such an annealing temperature, defects such as corrosion of the wiring layer result, thereby lowering the reliability of the semiconductor device.
There is an additional problem in the conventional method which utilizes the grinding process for the interlayer insulating film. First, when a P--SiO film 407 is formed by the plasma CVD method, if the space between lines of the aluminum electrodes 403 is narrow and the aspect ratio of the electrode is high, the reactive gas cannot flow smoothly into the space between the wiring composed of aluminum electrodes 403. In this case, the reactive gas molecules fail to reach the bottom of the space between the wiring, and as a result, the growth rate of the P--SiO film 407 is at a maximum at the upper corner of the metal wiring and tends to gradually diminish with increasing depth in the spaces between wiring. If the P--SiO film continues to grow, the film thickness increases rapidly at the upper corner portions of the wiring. The gradually overhanging growth at corner portions on opposite sides of a space eventually contact, thereby causing a void between the wiring.
When a void is formed in the interlayer insulating film, contaminant may be trapped in the void, resulting in the serious degradation of the reliability of the semiconductor device. Particularly, there is a probability that abrasives used in a succeeding grinding process of the insulating film will be trapped in the voids, thereby causing deterioration of the quality.